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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7723 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 16-bit, 1.2 msps cmos, sigma-delta adc functional block diagram agnd av dd dgnd vin(+) vin(C) ref2 xtal clkin mode 1 stby sync cfmt/ rd dgnd/ drdy dgnd/ db1 doe/ db4 sfmt/ db5 fsi/ db6 sco/ db7 modulator fir filter xtal clock AD7723 dgnd/ db2 dgnd/ db3 sdo/ db8 dgnd/db0 control logic dv dd / cs mode 2 half_pwr uni dgnd/db14 dgnd/db15 scr/db13 sldr/db12 slp/db11 tsi/db10 fso/db9 xtal_off 2.5v reference ref1 dv dd features 16-bit sigma-delta adc 1.2 msps output word rate 32/16 3 oversampling ratio low-pass and band-pass digital filter linear phase on-chip 2.5 v voltage reference standby mode flexible parallel or serial interface crystal oscillator single +5 v supply general description the AD7723 is a complete 16-bit, sigma-delta adc. the part operates from a +5 v supply. the analog input is continuously sampled, eliminating the need for an external sample-and-hold. the modulator output is processed by a finite impulse response (fir) digital filter. the on-chip filtering combined with a high oversampling ratio reduces the external antialias requirements to first order in most cases. the digital filter frequency response can be programmed to be either low pass or band pass. the AD7723 provides 16-bit performance for input bandwidths up to 460 khz at an output word rate up to 1.2 mhz. the sample rate, filter corner frequencies and output word rate are set by the crystal oscillator or external clock frequency. data can be read from the device in either serial or parallel format. a stereo mode allows data from two devices to share a single serial data line. all interface modes offer easy, high speed connections to modern digital signal processors. the part provides an on-chip 2.5 v reference. alternatively, an external reference can be used. a power-down mode reduces the idle power consumption to 200 m w. the AD7723 is available in a 44-lead pqfp package and is specified over the industrial temperature range from C40 c to +85 c. two input modes are provided, allowing both unipolar and bipolar input ranges.
C2C rev. 0 AD7723Cspecifications 1 b version parameter test conditions/comments min typ max units dynamic specifications 2, 3 half_pwr = 0 or 1 f clkin = 10 mhz when half-pwr = 1 decimate by 32 bipolar mode signal to noise full power 2.5 v reference 87 90 db 3 v reference 88.5 91 db half power 86.5 89 db total harmonic distortion 4 C96 C90 db spurious free dynamic range 4 2.5 v reference C92 db 3 v reference C90 db unipolar mode signal to noise 87 db total harmonic distortion 4 C89 db spurious free dynamic range 4 C90 db bandpass filter mode bipolar mode signal to noise 76 79 db decimate by 16 bipolar mode signal to noise measurement bandwidth = 0.383 f o 2.5 v reference 82 86 db 3 v reference 83 87 db signal to noise measurement bandwidth = 0.5 f o 78 81.5 db total harmonic distortion 4 2.5 v reference C88 db 3 v reference C86 db spurious free dynamic range 4 2.5 v reference C90 db 3 v reference C88 db unipolar mode signal to noise measurement bandwidth = 0.383 f o 84 db signal to noise measurement bandwidth = 0.5 f o 81 db total harmonic distortion 4 C89 db digital filter response low pass decimate by 32 0 khz to f clkin /83.5 0.001 db f clkin /66.9 C3 db f clkin /64 C6 db f clkin /51.9 to f clkin /2 C90 db group delay 1293/2f clkin settling time 1293/f clkin low pass decimate by 16 0 khz to f clkin /41.75 0.001 db f clkin /33.45 C3 db f clkin /32 C6 db f clkin /25.95 to f clkin /2 C90 db group delay 541/2f clkin settling time 541/f clkin band pass decimate by 32 f clkin /51.90 to f clkin /41.75 0.001 db f clkin /62.95, f clkin /33.34 C3 db f clkin /64, f clkin /32 C6 db 0 khz to f clkin /83.5, f clkin /25.95 to f clkin /2 C90 db group delay 1293/2f clkin settling time 1293/f clkin output data rate, f o decimate by 32 f clkin /32 decimate by 16 f clkin /16 analog inputs full-scale input span vin(+) C vin(C) bipolar mode 4/5 v ref2 v unipolar mode 0 8/5 v ref2 v (av dd = dv dd = +5 v 6 5%; agnd = agnd1 = agnd2 = dgnd = 0 v; f clkin = 19.2 mhz; ref2 = 2.5 v; t a = t min to t max ; unless otherwise noted)
C3C rev. 0 AD7723 b version parameter test conditions/comments min typ max units analog inputs (continued) absolute input voltage vin(+) and/or vin(C) agnd av dd v input sampling capacitance 2pf input sampling rate, f clkin 19.2 mhz clock clkin duty ratio 45 55 % reference ref1 output resistance 3k w using internal reference ref2 output voltage 2.39 2.54 2.69 v ref2 output voltage drift 60 ppm/ c using external reference ref2 input impedance ref1 = agnd 4 k w ref2 external voltage range 1.2 2.5 3.15 v static performance resolution 16 bits differential nonlinearity guaranteed monotonic 0.5 1 lsb integral nonlinearity 2 lsb dc cmrr 80 db offset error 20 mv gain error 5 0.5 % fsr logic inputs (excluding clkin) v inh , input high voltage 2.0 v v inl , input low voltage 0.8 v clock input (clkin) v inh , input high voltage 3.8 v v inl , input low voltage 0.4 v all logic inputs i in , input current v in = 0 v to dv dd 10 m a c in , input capacitance 10 pf logic outputs v oh , output high voltage |i out | = 200 m a 4.0 v v ol , output low voltage |i out | = 1.6 ma 0.4 v power supplies av dd 4.75 5.25 v i avdd half_pwr = logic low 50 60 ma half_pwr = logic high 25 33 ma dv dd 4.75 5.25 v i dvdd half_pwr = logic low 25 35 ma half_pwr = logic high 15 20 ma power consumption 6 standby mode 200 m w notes 1 operating temperature range is as follows: b version: C40 c to +85 c. 2 typical values for snr apply for parts soldered directly to a printed circuit board ground plane. 3 dynamic specifications apply for input signal frequencies from dc to 0.0240 f clkin in decimate by 16 mode and from dc to 0.0120 f clkin in decimate by 32 mode. 4 when using the internal reference, thd and sfdr specifications apply only to input signals above 10 khz with a 10 m f decoupling capacitor between ref2 and agnd2. at frequencies below 10 khz, thd degrades to 84 db and sfdr degrades to 86 db. 5 gain error excludes reference error. 6 clkin and digital inputs static and equal to 0 or dv dd . specifications subject to change without notice.
AD7723 C4C rev. 0 (av dd = dv dd = +5 v 6 5%; agnd = agnd1 = dgnd = 0 v; f clkin = 19.2 mhz; c l = 50 pf; sfmt = logic low or high, cfmt = logic low or high; t a = t min to t max unless otherwise noted) timing specifications parameter symbol min typ max units clkin frequency f clk 1 19.2 mhz clkin period (t clk = 1/f clk )t 1 0.052 1 m s clkin low pulsewidth t 2 0.45 t 1 0.55 t 1 clkin high pulsewidth t 3 0.45 t 1 0.55 t 1 clkin rise time t 4 5ns clkin fall time t 5 5ns fsi setup time t 6 05ns fsi hold time t 7 05ns fsi high time 1 t 8 1t clk clkin to sco delay t 9 25 40 ns sco period 2 , scr = 1 t 10 2t clk sco period 2 , scr = 0 t 10 1t clk sco transition to fso high delay t 11 05 ns sco transition to fso low delay t 12 05 ns sco transition to sdo valid delay t 13 512 ns sco transition from fsi 3 t 14 60 t clk + t 2 sdo enable delay time t 15 520 ns sdo disable delay time t 16 520 ns drdy high time 2 t 17 2t clk conversion time 2 (refer to tables i and ii) t 18 16/32 t clk clkin to drdy transition t 19 35 50 ns clkin to data valid t 20 20 35 ns cs / rd setup time to clkin t 21 0ns cs / rd hold time to clkin t 22 20 ns data access time t 23 20 35 ns bus relinquish time t 24 20 35 ns sync input pulsewidth t 25 1t clk sync low time before clkin rising t 26 0ns drdy high delay after rising sync t 27 25 35 ns drdy low delay after sync low t 28 2049 t clk notes 1 fso pulses are gated by the release of fsi (going low). 2 guaranteed by design. 3 frame sync is initiated on the falling edge of clkin. specifications subject to change without notice. i ol 1.6ma +1.6v c l 50pf to output pin i oh 200 m a figure 1. load circuit for timing specifications
AD7723 C5C rev. 0 clkin fsi sco 2.3v t 4 t 5 t 7 t 6 t 9 t 3 t 2 t 1 t 10 t 9 t 8 0.8v figure 2. serial mode timing for clock input, frame sync input and serial clock output clkin fsi (sfmt = 1) sco (cfmt = 0) fso (sfmt = 0) fso (sfmt = 1) sdo 32 clkin cycles t 8 t 11 t 12 t 13 t 14 t 11 d15 d14 d13 d2 d1 d0 d15 d14 figure 3. serial mode 1. timing for frame sync input, frame sync output, serial clock output and serial data output (refer to table i for control inputs, tsi = doe) d2 d1 d0 d15 d14 d13 d12 d11 d5 d4 d3 d2 d1 d0 d15 d14 t 8 t 11 t 12 t 13 t 14 32 clkin cycles clkin fsi sco (cfmt = 0) fso sdo figure 4. serial mode 2. timing for frame sync input, frame sync output, serial clock output and serial data output (refer to table i for control inputs, tsi = doe)
AD7723 C6C rev. 0 d2 d1 d0 d15 d14 d13 d12 d11 d5 d4 d3 d2 d1 d0 d15 d14 t 11 t 12 t 13 t 14 16 clkin cycles clkin fsi sco (cfmt = 0) fso sdo t 8 figure 5. serial mode 3. timing for frame sync input, frame sync output, serial clock output and serial data output (refer to table i for control inputs, tsi = doe) table i. serial interface (mode1 = 0, mode2 = 0) decimation digital filter sco frequency output data control inputs serial mode ratio (sldr) mode (slp) (scr) rate sldr slp scr 1 32 low pass f clkin f clkin /32 1 1 0 1 32 band pass f clkin f clkin /32 1 0 0 2 32 low pass f clkin /2 f clkin /32 1 1 1 2 32 band pass f clkin /2 f clkin /32 1 0 1 3 16 low pass f clkin f clkin /16 0 1 0 table ii. parallel interface digital filter decimation output control inputs mode ratio data rate mode1 mode2 band pass 32 f clkin /32 0 1 low pass 32 f clkin /32 1 0 low pass 16 f clkin /16 1 1 t 16 t 15 doe sdo figure 6. serial mode timing for data output enable and serial data output
AD7723 C7C rev. 0 t 19 t 20 word n word n C 1 word n + 1 t 18 t 17 t 19 clkin drdy db0Cdb15 figure 7a. parallel mode read timing, cs and rd tied logic low t 18 t 19 t 24 t 22 t 21 t 22 t 23 t 21 t 19 valid data clkin drdy rd/cs db0Cdb15 figure 7b. parallel mode read timing, cs = rd t 26 t 27 t 25 t 28 clkin sync drdy figure 8. sync timing
AD7723 C8C rev. 0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7723 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* (t a = +25 c unless otherwise noted) dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v av dd , av dd1 to agnd . . . . . . . . . . . . . . . . . C0.3 v to +7 v av dd , av dd1 to dv dd . . . . . . . . . . . . . . . . . . . C1 v to +1 v agnd, agnd1 to dgnd . . . . . . . . . . . . C0.3 v to +0.3 v digital inputs to dgnd . . . . . . . . . C0.3 v to dv dd + 0.3 v digital outputs to dgnd . . . . . . . . C0.3 v to dv dd + 0.3 v vin(+), vin(C) to agnd . . . . . . . . C0.3 v to av dd + 0.3 v ref1 to agnd . . . . . . . . . . . . . . . . C0.3 v to av dd + 0.3 v ref2 to agnd . . . . . . . . . . . . . . . . C0.3 v to av dd + 0.3 v operating temperature range . . . . . . . . . . C 40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . +150 c q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . . 95 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package package model range description option AD7723bs C40 c to +85 c plastic quad flatpack s-44 pin configuration 44-lead pqfp package 12 13 14 15 16 17 18 19 2 0 21 22 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 pin 1 identifier top view (not to scale) 29 30 31 32 27 28 25 26 23 24 33 scr/db13 dgnd/db14 doe/db4 dgnd/db15 sfmt/db5 dv dd / cs fsi/db6 sync sco/db7 dgnd dv dd stby sdo/db8 av dd fso/db9 clkin tsi/db10 xtal slp/db11 xtal_off sldr/db12 half_pwr agnd agnd dgnd/db2 dgnd/db1 dgnd/db0 cfmt/ rd dgnd/ drdy dgnd mode2 mode1 agnd1 agnd1 av dd1 av dd agnd uni ref2 vin(C) vin(+) ref1 agnd2 AD7723 dgnd/db3 warning! esd sensitive device
AD7723 C9C rev. 0 pin function descriptions mnemonic pin no. description av dd1 11 digital logic power supply voltage for the analog modulator. agnd1 9, 10 digital logic power supply ground for the analog modulator. av dd 17, 26 positive power supply voltage for the analog modulator. agnd 16, 18, 25 power supply ground for the analog modulator. agnd2 22 power supply ground return to the reference circuitry, ref2, of the analog modulator. dv dd 39 digital power supply voltage; +5 v 5%. dgnd 6, 28 ground reference for digital circuitry. ref1 21 reference output. ref1 connects through 3 k w to the output of the internal 2.5 v reference and to a buffer amplifier that drives the s-d modulator. ref2 23 reference input. ref2 connects to the output of an internal buffer amplifier that drives the s-d modulator. when ref2 is used as an input, ref1 must be connected to agnd to disable the inter- nal buffer amplifier. vin(+) 20 positive terminal of the differential analog input. vin(C) 19 negative terminal of the differential analog input. uni 24 analog input range select input. the uni pin selects the analog input range for either bipolar or unipo- lar operation. a logic high input selects unipolar operation and a logic low selects bipolar operation. clkin 12 clock input. an external clock source can be applied directly to this pin with xtal_off tied high. alternatively, a parallel resonant fundamental frequency crystal, in parallel with a 1 m w resistor can be connected between the xtal pin and the clkin pin with xtal_off tied low. external capacitors are then required from the clkin and xtal pins to ground. consult the crystal manufac turers recommendation for the load capacitors. xtal 13 input to crystal oscillator amplifier. if an external clock is used, xtal should be tied to agnd1. xtal_off 14 oscillator enable input. a logic high disables the crystal oscillator amplifier to allow use of an exter- nal clock source. set low when using an external crystal between the clkin and xtal pins. mode1/2 8, 7 mode control inputs. the mode1 and mode2 pins choose either parallel or serial data interface operation and select the operating mode for the digital filter in parallel mode. refer to tables i and ii. half_pwr 15 when set high, the power dissipation is reduced by approximately one-half and a maximum clkin frequency of 10 mhz applies. sync 29 synchronization logic input. when using more than one AD7723, operated from a common master clock, sync allows each adc to simultaneously sample its analog input and update its output register. a rising edge resets the AD7723 digital filter sequencer counter to zero. when the rising edge of clkin senses a logic low on sync, the reset state is released. because the digital filter and sequencer are completely reset during this action, sync pulses cannot be applied continuously. stby 27 standby logic input. a logic high sets the AD7723 into the power-down state.
AD7723 C10C rev. 0 parallel mode pin function descriptions mnemonic pin no. description dv dd / cs 30 chip select logic input. cfmt/ rd 4 read logic input. used in conjunction with cs to read data from the parallel bus. the output data bus is enabled when the rising edge of clkin senses a logic low level on rd if cs is also low. when rd is sensed high, the output data bits, db15Cdb0 will be high impedance. dgnd/ drdy 5 data ready logic output. a falling edge indicates a new output word is available to be read from the output data register. drdy will return high upon completion of a read operation. if a read operation does not occur between output updates, drdy will pulse high for two clkin cycles before the next output update. drdy also indicates when conversion results are available after a sync sequence. dgnd/db15 31 data output bit, (msb) dgnd/db14 32 data output bit. scr/db13 33 data output bit. sldr/db12 34 data output bit. slp/db11 35 data output bit. tsi/db10 36 data output bit. fso/db9 37 data output bit. sdo/db8 38 data output bit. sco/db7 40 data output bit. fsi/db6 41 data output bit. sfmt/db5 42 data output bit. doe/db4 43 data output bit. dgnd/db3 44 data output bit. dgnd/db2 1 data output bit. dgnd/db1 2 data output bit. dgnd/db0 3 data output bit, (lsb).
AD7723 C11C rev. 0 serial mode pin function descriptions mnemonic pin no. description cfmt/ rd 4 serial clock format logic input. the clock format pin selects whether the serial data, sdo, is valid on the rising or falling edge of the serial clock, sco. when cfmt is logic low, serial data is valid on the falling edge of the serial clock, sco. if cfmt is logic high, sdo is valid on the rising edge of sco. doe/db4 43 data output enable logic input. the doe pin controls the three-state output buffer of the sdo pin. the active state of doe is determined by the logic level on the tsi pin. when the doe logic level equals the level on the tsi pin the serial data output, sdo, is active. otherwise sdo will be high impedance. sdo can be three-state after a serial data transmission by connecting doe to fso. in normal operations, tsi and doe should be tied low. sfmt/db5 42 serial data format logic input. the logic level on the sfmt pin selects the format of the fso signal for serial mode 1. a logic low makes the fso output a pulse, one sco cycle wide at the beginning of a serial data transmission. with sfmt set to a logic high, the fso signal is a frame pulse that is active low for the duration of the 16-bit transmission. for serial modes 2 and 3, sfmt should be tied high. fsi/db6 41 frame synchronization logic input. the fsi input is used to synchronize the AD7723 serial output data register to an external source and to allow more than one AD7723, operated from a common master clock, to simultaneously sample its analog input and update its output register. sco/db7 40 serial clock output. sdo/db8 38 serial data output. the serial data is shifted out msb first, synchronous with the sco. serial mode 1 data transmissions last 32 sco cycles. after the lsb is output, trailing zeros are output for the remaining 16 sco cycles. serial modes 2 and 3 data transmissions last 16 sco cycles. fso/db9 37 frame sync output. fso indicates the beginning of a word transmission on the sdo pin. depend- ing on the logic level of the sfmt pin, the fso signal is either a positive pulse approximately one sco period wide, or a frame pulse which is active low for the duration of the 16-data bit transmission. tsi/db10 36 time slot logic input. the logic level on tsi sets the active state of the doe pin. with tsi set logic high, doe will enable the sdo output buffer when it is a logic high, and vice versa. tsi is used when two AD7723s are connected to the same serial data bus. when this function is not needed, tsi and doe should be tied low. slp/db11 35 serial mode low pass/band pass filter select input. with slp set logic high, the low-pass filter response is selected. a logic low selects band pass. sldr/db12 34 serial mode low/high output data rate select input. with sldr set logic high, the low data rate is selected. a logic low selects the high data rate. the high data rate corresponds to data at the out- put of the fourth decimation filter (decimate by 16). the low data rate corresponds to data at the output of the fifth decimation filter (decimate by 32). scr/db13 33 serial clock rate select input. with scr set logic low, the serial clock output frequency, sco, is equal to the clkin frequency. a logic high sets it equal to one-half the clkin frequency. dv dd / cs 30 tie to dv dd . dgnd/db14 32 tie to dgnd. dgnd/db15 31 tie to dgnd. dgnd/ drdy 5 tie to dgnd. dgnd/db0 3 tie to dgnd. dgnd/db1 2 tie to dgnd. dgnd/db2 1 tie to dgnd. dgnd/db3 44 tie to dgnd.
AD7723 C12C rev. 0 terminology signal-to-noise ratio (snr) snr is the measured signal-to-noise ratio at the output of the adc. the signal is the rms magnitude of the fundamental. noise is the rms sum of all of the nonfundamental signals up to half the output data rate (f o /2), excluding dc. the adc is evaluated by applying a low noise, low distortion sine wave signal to the input pins. by generating a fast fourier transform (fft) plot, the snr data can then be obtained from the out- put spectrum. total harmonic distortion (thd) thd is the ratio of the rms sum of the harmonics to the rms value of the fundamental. thd is defined as: thd = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through sixth harmonics. the thd is also derived from the fft plot of the adc output spectrum. spurious free dynamic range (sfdr) defined as the difference, in db, between the peak spurious or harmonic component in the adc output spectrum (up to f o /2 and excluding dc) and the rms value of the fundamental. normally, the value of this specification will be determined by the largest harmonic in the output spectrum of the fft. for input signals whose second harmonics occur in the stop band region of the digital filter, the spur in the noise floor limits the sfdr. passband ripple the frequency response varia tion of the AD7723 in the defined passband frequency range. passband frequency the frequency up to which the frequency response variation is within the passband ripple specification. cutoff frequency the frequency below which the AD7723s frequency response will not have more than 3 db of attenuation. stopband frequency the frequency above which the AD7723s frequency response will be within its stopband attenuation. stopband attenuation the AD7723s frequency response will not have less than 90 db of attenuation in the stated frequency band. integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the endpoints of the transfer function are minus full scale, a point 0.5 lsb below the first code transition (100 . . . 00 to 100 . . . 01 in bipolar mode, 000 . . . 00 to 000 . . . 01 in unipolar mode) and plus full scale, a point 0.5 lsb above the last code transi- tion (011 . . . 10 to 011 . . . 11 in bipolar mode, 111 . . . 10 to 111 . . . 11 in unipolar mode). the error is expressed in lsbs. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between two adjacent codes in the adc. common-mode rejection ratio the ability of a device to reject the effect of a voltage applied to both input terminals simultaneouslyoften through variation of a ground levelis specified as a commonCmode rejection ratio. cmrr is the ratio of gain for the differential signal to the gain for the common-mode signal. unipolar offset error unipolar offset error is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal differential voltage (vin(+) C vin(C)+ 0.5 lsb) when operating in the unipolar mode. bipolar offset error this is the deviation of the midscale transition code (111 . . . 11 to 000 . . . 00) from the ideal differential voltage (vin(+) C vin(C) C 0.5 lsb) when operating in the bipolar mode. gain error the first code transition should occur at an analog value 1/2 lsb above Cfull scale. the last transition should occur for an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.
AD7723 C13C rev. 0 typical performance characteristicsC analog input level C db 110 40 C28 2 C23 db C18 C13 C8 C3 100 90 80 60 50 70 snr thd sfdr signal frequency = 98khz measurement bandwidth = 460khz figure 9. snr, thd and sfdr vs. analog input level relative to full scale (output data rate = 1.2 mhz) analog input level C db 110 40 C28 2 C23 db C18 C13 C8 C3 100 90 80 60 50 70 snr thd sfdr signal frequency = 98khz measurement bandwidth = 300khz figure 10. snr, thd and sfdr vs. analog input level relative to full scale (output data rate = 600 khz) 102 100 84 db 92 90 88 86 96 94 98 temperature C 8 c 100 C250 255075 C50 signal frequency = 98khz measurement bandwidth = 460khz snr thd 3rd 2nd figure 11. snr and thd vs. temperature (output data rate = 1.2 mhz) 106 104 88 db 96 94 92 90 100 98 102 temperature C 8 c 100 C250 255075 C50 snr thd 2nd 3rd signal frequency = 98khz measurement bandwidth = 300khz figure 12. snr and thd vs. temperature (output data rate = 600 khz) output word rate C khz 106 92 100 500 db 1000 1500 2150 104 102 100 96 94 98 snr thd sfdr 90 88 86 84 input signal = 10khz measurement bandwidth = 0.383 3 owr figure 13. snr, thd and sfdr vs. sampling frequency (decimate by 16) output word rate C khz 115 90 50 150 db 300 600 900 110 105 95 100 snr thd sfdr input signal = 10khz measurement bandwidth = 0.5 3 owr 450 750 figure 14. snr, thd and sfdr vs. sampling frequency (decimate by 32) (av dd = dv dd = 5 v; t a = +25 8 c; clkin = 19.2 mhz; external +2.5 v reference, unless otherwise noted)
AD7723 C14C rev. 0 code 2000 0 32700 32713 32702 frequency of occurrence 32704 32706 32708 32710 32712 1800 800 600 400 200 1400 1000 1600 1200 v in (+) = v in (C) 8192 samples taken figure 15. histogram of output codes with dc input (output data rate = 1.2 mhz) code 5000 0 32703 32710 32704 frequency of occurrence 32705 32706 32707 32708 32709 4500 2000 1500 1000 500 3500 2500 4000 3000 v in (+) = v in (C) 8192 samples taken figure 16. histogram of output codes with dc input (output data rate = 600 khz) 1.00 0.80 C0.80 0 65535 16384 32768 49152 0.20 C0.20 C0.40 C0.60 0.60 0.40 0.00 C1.00 67108864 samples taken differential mode code dnl error C lsb figure 17. differential nonlinearity (output data rate = 1.2 mhz) 1.00 0.80 C0.80 0 65535 16384 32768 49152 0.20 C0.20 C0.40 C0.60 0.60 0.40 0.00 C1.00 67108864 samples taken differential mode code dnl error C lsb figure 18. differential nonlinearity (output data rate = 600 khz) 1.00 0.80 C0.80 0 65535 16384 32768 49152 0.20 C0.20 C0.40 C0.60 0.60 0.40 0.00 C1.00 67108864 samples taken differential mode code inl error C lsb figure 19. integral nonlinearity (output data rate = 1.2 mhz) 1.00 0.80 C0.80 0 65535 16384 32768 49152 0.20 C0.20 C0.40 C0.60 0.60 0.40 0.00 C1.00 67108864 samples taken differential mode code inl error C lsb figure 20. integral nonlinearity (output data rate = 600 khz)
AD7723 C15C rev. 0 clock frequency C mhz 225 150 0 0 25 power C mw 5 101520 200 175 125 100 ai dd (half_power = 1) di dd ai dd (half_power = 0) 75 50 25 figure 21. power consumption vs. clkin frequency 0 C150 0e+0 600e+3 100e+3 200e+3 300e+3 400e+3 500e+3 C25 C50 C75 C100 C125 snr = C86.19db snr&d = C85.9db thd = C96.42db sfdr = C99.61db 2nd harmonic = C100.98db 3rd harmonic = C99.61db a in = 100khz measured bw = 460khz power level relative to full scale C db frequency C hz figure 22. 16k point fft (output data rate = 1.2 mhz) 0 C120 0e+0 300e+3 50e+3 100e+3 150e+3 200e+3 250e+3 C20 C40 C60 C80 C100 snr = C89.91db snr&d = C89.7db thd = C101.16db sfdr = C102.1db 2nd harmonic = C102.1db 3rd harmonic = C110.3db a in = 50khz measured bw = 300khz C140 C160 power level relative to full scale C db frequency C hz figure 23. 16k point fft (output data rate = 600 khz) circuit description the AD7723 adc employs a sigma-delta conversion technique to convert the analog input into an equivalent digital word. the modulator samples the input waveform and outputs an equiva- lent digital word at the input clock frequency, f clkin . due to the high oversampling rate, which spreads the quantiza- tion noise from 0 to f clkin /2, the noise energy contained in the band of interest is reduced (figure 24a). to further reduce the quantization noise, a high order modulator is employed to shape the noise spectrum, so that most of the noise energy is shifted out of the band of interest (figure 24b). the digital filter that follows the modulator removes the large out-of-band qua ntization noise, (figure 24c) while also reduc- ing the data rate from f clkin at the input of the filter to f clkin /32 or f clkin /16 at the output of the filter, depending on the state on the mode1/2 pins in parallel interface mode or the pin sldr in serial interface mode. the AD7723 output data rate is a little over twice the signal bandwidth, which guarantees that there is no loss of data in the signal band. digital filtering has certain advantages over analog filtering. firstly, since digital filtering occurs after the a/d conversion, it can remove noise injected during the conversion process. ana- log filtering cannot remove noise injected during conversion. secondly, the digital filter combines low passband ripple with a steep roll-off, while also maintaining a linear phase response. noise shaping quantization noise digital filter cutoff frequency f clkin /2 f clkin /2 f clkin /2 band of interest band of interest band of interest (a) (b) (c) figure 24. sigma-delta adc the AD7723 employs four or five finite impulse response (fir) filters in series. each individual filters output data rate is half that of the filters input data rate. when data is fed to the interface from the output of the fourth filter, the output data rate is f clkin /16 and the resulting over sampling ratio (osr) of the converter is 16. data fed to the interface from the output of the fifth filter results in an output data rate of f clkin /32 and a corresponding osr for the converter of 32. when an output data rate (odr) of f clkin /32 is selected, the digital filter re- sponse can be set to either low-pass or band-pass. the band- pass response is useful when the input signal is band limited since the resulting output data rate is half that required to con- vert the band when the low pass operating mode is used. to illustrate the operation of this mode, consider a band-limited signal as shown in figure 25a. this signal band can be correctly converted by selecting the (low pass) odr = f clkin /16 mode, as shown in figure 25b. note that the output data rate is a little over twice the maximum frequency in the frequency band. alterna- tively the band-pass mode can be selected as shown in figure 25c. the band-pass filter removes unwanted signals from dc to just below f clkin /64. rather than outputting data at f clkin /16, the output of the band-pass filter is sampled at f clkin /32. this
AD7723 C16C rev. 0 effectively translates the wanted band to a maximum frequency of a little less than f clkin /64 as shown in figure 25d. halving the output data rate reduces the work load of any following signal processor and also allows a lower serial clock rate to be used. band limited signal 0db f clkin /16 0db odr low pass filter response sample image f clkin /16 low pass filter. output data rate = f clkin /16 0db f clkin /16 sample image band-pass filter response band-pass filter. f clkin /16 low pass filter. output data rate = f clkin /32 odr sample image frequency translated input signal 0db (a) (b) (c) (d) figure 25. band-pass operation the frequency response of the three digital filter operating modes is shown in figures 26a, 26b, and 26c. f clkin 0.0 1.0 0.5 0db C100db figure 26a. low-pass filter decimate by 16 f clkin 0.0 1.0 0.5 0db C100db figure 26b. low-pass filter decimate by 32 f clkin 0.0 1.0 0.5 0db C100db figure 26c. band-pass filter decimate by 32 figure 27a shows the frequency response of the digital filter in both low-pass and band-pass modes. due to the sampling nature of the converter, the pass-band response is repeated about the input sampling frequency, f clkin and at integer mul- tiples of f clkin . out-of-band noise or signals coincident with any of the filter images are aliased down to the passband. how- ever, due to the AD7723s high oversampling ratio, these bands occupy only a small fraction of the spectrum, and most broad- band noise is attenuated by at least 90 db. in addition, as shown in figure 27b, with even a low order filter, there is significant attenuation at the first image frequency. this contrasts with a normal nyquist rate converter where a very high order antialias filter is required to allow most of the band width to be used while ensuring sufficient attenuation at multiples of f clkin . 1f clkin 2f clkin 3f clkin 0db figure 27a. digital filter frequency response f clkin /32 0db f clkin required attenuation antialias filter response output data rate figure 27b. frequency response of antialias filter
AD7723 C17C rev. 0 applying the AD7723 analog input range the AD7723 has differential inputs to provide common-mode noise rejection. in unipolar mode the analog input range is 0 to 8/5 v ref2 , while in bipolar mode the analog input range is 4/5 v ref2 . the output code is twos complement binary in both modes with 1 lsb = 61 m v. the ideal input/output trans- fer characteristics for the two modes are shown in figure 28 below. in both modes the absolute voltage on each input must remain within the supply range agnd to av dd . the bipolar mode allows either single-ended or complementary input signals. 011111 011110 000010 000001 000000 111111 111110 100000 100001 C4/5 3 v ref2 0v +4/5 3 v ref2 C 1lsb bipolar (0v) (+4/5 3 v ref2 ) (+8/5 3 v ref2 C 1lsb) unipolar figure 28. bipolar (unipolar) mode transfer function the AD7723 will accept full-scale inband signals, however, large scale out of band signals can overload the modulator in- puts. figure 29 shows the maximum input signal level as a func- tion of frequency. a minimal single-pole rc antialias filter set to f clkin /24 will allow full-scale input signals over the entire frequency spectrum. input signal frequency relative to f clkin 0 0.5 0.02 0.04 0.06 0.08 0.10 0.12 0.14 2.200 2.100 1.300 peak input C v pk 1.700 1.600 1.500 1.400 1.900 1.800 2.000 v ref = 2.5v figure 29. peak input signal level vs. signal frequency analog input the analog input of the AD7723 uses a switched capacitor technique to sample the input signal. for the purpose of driving the AD7723, an equivalent circuit of the analog inputs is shown in figure 30. for each half clock cycle, two highly linear sam- pling capacitors are switched to both inputs, converting the input signal into an equivalent sampled charge. a signal source driving the analog inputs must be able to source this charge, while also settling to the required accuracy by the end of each half-clock phase. 500 v 500 v AD7723 clkin vin(+) vin(C) ac ground 2pf 2pf f a f b f a f b f a f b f a f b figure 30. analog input equivalent circuit driving the analog inputs to interface the signal source to the AD7723, at least one op amp will generally be required. choice of op amp will be critical to achieving the full performance of the AD7723. the op amp not only has to recover from the transient loads that the adc imposes on it, but must also have good distortion characteristics and very low input noise. resistors in the signal path will also add to the overall thermal noise floor, necessitating the choice of low value resistors. placing an rc filter between the drive source and the adc inputs, as shown in figure 31, has a number of beneficial af- fects: transients on the op amp outputs are significantly reduced since the external capacitor now supplies the instantaneous charge required when the sampling capacitors are switched to the adc input pins and, input circuit noise at the sample im- ages is now significantly attenuated resulting in improved over- all snr. the external resistor serves to isolate the external capacitor from the adc output, thus improving op amp stabil- ity while also isolating the op amp output from any remaining transients on the capacitor. by experimenting with different filter values, the optimum performance can be achieved for each application. as a guideline, the rc time constant (r c) should be less than a quarter of the clock period to avoid non- linear currents from the adc inputs being stored on the exter- nal capacitor and degrading distortion. this restriction means that this filter cannot form the main antialias filter for the adc. vin(+) vin(C) AD7723 r r c figure 31. input rc network with the unipolar input mode selected, just one op amp is re- quired to buffer single ended input signals. however, driving the AD7723 with complementary signals and with the bipolar input range selected has some distinct advantages: even order harmonics in both the drive circuits and the AD7723 front end are attenuated; and the peak to peak input signal range on both inputs is halved. halving the input signal range allows some op amps to be powered from the same supplies as the AD7723. although a complementary driver will require the use of two op amps per adc, it may avoid the need to generate additional supplies just for these op amps.
AD7723 C18C rev. 0 figures 32 and 33 show two such circuits for driving the AD7723. figure 32 is intended for use when the input signal is biased about 2.5 v while figure 33 is used when the input signal is biased about ground. while both circuits convert the input signal into a complementary signal, the circuit in figure 33 also level shifts the signal so that both outputs are biased about 2.5 v. suitable op amps include the ad8047, ad8044, ad8041 and its dual equivalent the ad8042. the ad8047 has lower input noise than the ad8041/42 but has to be supplied from a +7.5 v/ C2.5 v supply. the ad8041/ad8042 will typically degrade snr from 90 db to 88 db but can be powered from the same single +5 v supply as the AD7723. ad8047 ad8047 10k v 220 v 27 v 220pf a1 a2 vin(+) vin(C) ref1 ref2 AD7723 10nf 220nf 220 v 27 v ain = 6 2v biased about 2.5v r source 50 v 1 m f r in 390 v r fb 220 v gain = 2 3 r fb /(r source + r in ) figure 32. single-ended to differential input circuit for bipolar mode ope ration (analog input biased about +2.5 v) ad8047 ad8047 r fb 220 v 220 v 27 v 220pf a1 a2 vin(+) vin(C) ref1 ref2 AD7723 10nf 220nf 220 v 27 v ain = 6 2v biased about ground 1 m f r source 50 v r in 390 v r balance1 220 v gain = 2 3 r fb /(r in + r source ) r balance1 = r balance2 3 (r in + r source )/(2 3 r fb ) r ref2 = r ref1 3 (r in + r source )/r fb r ref1 10k v r ref2 20k v r balance2 r balance2 figure 33. single-ended to differential input circuit for bipolar mode operation (analog input biased about ground) applying the reference the reference circuitry used in the AD7723 includes an on-chip 2.5 v bandgap reference and a reference buffer circuit. the block diagram of the reference circuit is shown in figure 34. the internal reference voltage is connected to ref1 through a 3k w resistor and is internally buffered to drive the analog modulators switched cap dac (ref2). when using the inter- nal reference a 1 m f capacitor is required between ref1 and agnd to decouple the bandgap noise. if the internal reference is required to bias external circuits, use an external precision op amp to buffer ref1. comparator reference buffer 1v 1 m f ref2 ref1 2.5v reference switched-cap dac referenced AD7723 3k v figure 34. reference circuit block diagram where gain error or gain error drift requires the use of an exter- nal reference, the reference buffer in figure 34 can be turned off by grounding the ref1 pin and the external reference can be applied directly to pin ref2. the AD7723 will accept an exter- nal reference voltage between 1.2 v to 3.15 v. by applying a 3 v rather than a 2.5 v reference, snr is typically improved by about 1 db. where the output common-mode range of the amplifier driving the inputs is restricted, the full-scale input signal span can be reduced by applying a lower than 2.5 v refer- ence. for example, a 1.25 v reference would make the bipolar input span 1 v, but would degrade snr. in all cases, since the ref2 voltage connects to the analog modulator, a 220 nf and 10 nf capacitor must connect directly from ref2 to agnd. the external capacitor provides the charge required for the dynamic load presented at the ref2 pin (see figure 35). 10nf 220nf a b b a 4pf 4pf ref2 switched-cap dac referenced clkin a f f f f b a b f f f f figure 35. ref2 equivalent input circuit the ad780 is ideal to use as an external reference with the AD7723. figure 36 shows a suggested connection diagram. grounding pin 8 on the ad780 selects the 3 v output mode. 1 2 3 4 ad780 AD7723 ref2 ref1 +5v 1 m f 22nf 220nf 10nf 22 m f nc +v in temp gnd o/p select nc v out trim 2.5v nc = no connect 8 7 6 5 figure 36. external reference circuit connection
AD7723 C19C rev. 0 clock generation the AD7723 contains an oscillator circuit to allow a crystal or an external clock signal to generate the master clock for the adc. the connection diagram for use with a crystal is shown in figure 37. consult the manufacturers recommendation for the load capacitors. to enable the oscillator circuit on board the AD7723, xtal_off should be tied low. 1m v xtal clkin AD7723 figure 37. crystal oscillator connection when an external clock source is being used, the internal oscil- lator circuit can be disabled by tying xtal_off high. a low phase noise clock should be used to generate the adc sampling clock because sampling clock jitter effectively modulates the input signal and raises the noise floor. the sampling clock gen- erator should be isolated from noisy digital circuits, grounded and heavily decoupled to the analog ground plane. the sampling clock generator should be referenced to the ana- log ground in a split ground system. however, this is not always possible because of system constraints. in many applications, the sampling clock must be derived from a higher frequency multipurpose system clock that is generated on the digital ground plane. if the clock signal is passed between its origin on a digital ground plane to the AD7723 on the analog ground plane, the ground noise between the two planes adds directly to the clock and will produce excess jitter. the jitter can cause degradation in the signal-to-noise ratio and also produce un- wanted harmonics. this can be remedied somewhat by trans- mitting the sampling signal as a differential one, using either a small rf transformer or a high speed differential driver and a receiver such as pecl. in either case, the original master sys- tem clock should be generated from a low phase noise crystal oscillator. system synchronization the sync input provides a synchronization function for use in parallel or serial mode. sync allows the user to begin gathering samples of the analog input from a known point in time. this allows a system using multiple AD7723s, operated from a com- mon master clock, to be synchronized so that each adc simul- taneously updates its output register. in a system using multiple AD7723s, a common signal to their sync inputs will synchronize their operation. on the rising edge of sync, the digital filter sequencer is reset to zero. the filter is held in a reset state until a rising edge on clkin senses sync low. a sync pulse, one clkin cycle long, can be applied synchronous to the falling edge of clkin. this way, on the next rising edge of clkin, sync is sensed low, the filter is taken out of its reset state and multiple parts begin to gather input samples. following a sync, the modulator and filter need time to settle before data can be read from the AD7723. drdy goes high following a synchronization and it remains high until valid data is available at the interface. data interfacing the AD7723 offers a choice of serial or parallel data interface options to meet the requirements of a variety of system configu- rations. in parallel mode, multiple AD7723s can easily be con- figured to share a common data bus. serial mode is ideal when it is required to minimize the number of data interface lines connected to a host processor. in either case, careful attention to the system configuration is required to realize the high dy- namic range available with the AD7723. consult the recom- mendation in the layout and grounding section. the follo wing recommendations for parallel interfacing also apply for the sys- tem design when using the serial mode. parallel interface when using the AD7723, place a buffer/latch adjacent to the converter to isolate the converters data lines from any noise which may be on the data bus. even though the AD7723 has three state outputs, use of an isolation latch represents good design practice. figure 38 shows how the parallel interface of the AD7723 can be configured to interface with the system data bus of a micro- processor or a microcontroller such as the mc68hc16 or 8xc251. with cs and rd tied permanently low, the data out- put bits are always active. when drdy goes high for two clock cycles, the rising edge of drdy is used to latch the conversion data before a new conversion result is loaded into the output data register. the falling edge of drdy then sends an appropri- ate interrupt signal for interface control. alternatively, if buffers are used instead of latches, the falling edge of drdy provides the necessary interrupt when a new output word is available from the AD7723. dsp addr decode db0C15 drdy cs rd 16 16 oe d0C15 rd interrupt addr AD7723 74xx16374 figure 38. parallel interface connection
AD7723 C20C rev. 0 serial interface the AD7723s serial data interface can operate in three modes, depending on the application requirements. the timing dia- grams in figures 3, 4 and 5 show how the AD7723 may be used to transmit its conversion results. table i shows the control inputs required to select each serial mode, and the digital filter operating mode. the AD7723 operates solely in the master mode providing three serial data output pins for transfer of the conversion results. the serial data clock output, sco, serial data output, sdo, and frame sync output, fso, are all synchro- nous with clkin. fso is continuously output at the conversion rate of the adc. serial data shifts out of the sdo pin synchronous with sco. the fso is used to frame the output data transmission to an external device. an output data transmission is either 16 or 32 sco cycles in duration (refer to table i). serial data shifts out of the sdo pin, msb first, lsb last, for a duration of 16 sco cycles. in serial mode 1, sdo outputs zeros for the last 16 sco cycles of the 32-cycle data transmission frame. the clock format pin, cfmt, selects the active edge of sco. with cfmt tied logic low, the serial interface outputs fso and sdo change state on the sco rising edge and are valid on the falling edge of sco. with cfmt set high, fso and sdo change state on the falling sco edge and are valid on the sco rising edge. the frame sync input, fsi, can be used if the AD7723 conver- sion process must be synchronized to an external source. fsi allows the conversion data presented to the serial interface to be a filtered and decimated result derived from a known point in time. a common frame sync signal can be applied to two or more AD7723s to synchronize them to a common master clock. when fsi is applied for the first time, the digital filter sequencer counter is reset to zero, the AD7723 interrupts the current data transmission, reloads the output shift register, resets sco and transmits the conversion result. synchronization starts immedi- ately and the following conversions are invalid while the digital filter settles. fsi can be applied once after power-up, or it can be a periodic signal, synchronous to clkin, occurring every 32 clkin cycles. subsequent fsi inputs applied every 32 clkin cycles do not alter the serial data transmission and do not reset the digital filter sequencer counter. fsi is an optional signal; if synchronization is not required, fsi can be tied to a logic low and the AD7723 will generate fso outputs. in serial mode 1, the control input, sfmt, can be used to select the format for the serial data transmission (refer to figure 3). fso is either a pulse, approximately one sco cycle in dura- tion, or a square wave with a period of 32 sco cycles. with a logic low level on sfmt, fso pulses high for one sco cycle at the beginning of a data transmission frame. with a logic high level on sfmt, fso goes low at the beginning of a data trans- mission frame and returns high after 16 sco cycles. note that in serial mode 1, fsi can be used to synchronize the AD7723 if sfmt is set to a logic high. if sfmt is set low, the fsi input will have no effect on synchronization. in serial modes 2 and 3, sfmt should be tied high. tsi and doe should be tied low in these modes. the fso is a pulse, approximately one sco cycle in duration, occurring at the beginning of the serial data transmission. two-channel multiplexed operation two additional serial interface control pins, doe and tsi, are provided to allow the serial data outputs of two AD7723s, to easily share one serial data line when operating in serial mode 1. figure 39 shows the connection diagram. since a serial data transmission frame lasts 32 sco cycles, two adcs can share a single data line by alternating transmission of their 16-bit out- put data onto one sdo pin. AD7723 master AD7723 slave fsi sfmt tsi fsi clkin doe cfmt sdo sco fso clkin tsi cfmt sfmt doe sdo sco fso dv dd dv dd dgnd dgnd from control logic to host processor figure 39. serial mode 1 connection for two-channel multiplexed operation the data output enable pin, doe, controls the sdo output buffer. when the logic level on doe matches the state of the tsi pin, the sdo output buffer drives the serial data line, other- wise the output of the buffer goes high impedance. the serial format pin, sfmt, is set high to choose the frame sync output format. the clock format pin, cfmt, is set low so that serial data is made available on sdo after the rising edge of sco and can be latched on the sco falling edge. the master device is selected by setting tsi to a logic low and connecting its fso to doe. the slave device is selected with its tsi pin tied high and both its fsi and doe controlled from the masters fso. since the fso of the master controls the doe input of both the master and slave, one adcs sdo is active while the other is high impedance (figure 40). when the master transmits its conversion result during the first 16 sco cycles of a data transmission frame, the low level on doe sets the slaves sdo high impedance. once the master completes transmitting its conversion data, its fso goes high, triggers the slaves fsi to begin its data transmission frame. since fso pulses are gated by the release of fsi (going low) and the fsi of the slave device is held high during its data transmission, the fso from the master device must be used for connection to the host processor.
AD7723 C21C rev. 0 serial interface to dsps in serial mode, the AD7723 can be directly interfaced to several industry standard digital signal processors. in all cases, the AD7723 operates as the master with the dsp operating as the slave. the AD7723 provides its own serial clock (sco) to transmit the digital word on the sdo pin to the dsp. the AD7723 also generates the frame synchronization signal that synchronizes the transfer of the 16-bit word from the AD7723 to the dsp. depending on the serial mode used, sco will have a frequency equal to clkin or equal to clkin/2. when sco equals 19.2 mhz, the AD7723 can be interfaced to analog devices adsp-2106x sharc dsp. with a 19.2 mhz master clock and sco equal to clkin/2, the AD7723 can be inter- faced with the adsp-21xx family of dsps, the dsp56002 and the tms320c5x-57. when the AD7723 is used in the half_pwr mode, i.e., clkin is less than 10 mhz, then the AD7723 can be used with dsps such as the tms320c20/c25 and the dsp56000/1. AD7723-to-adsp-21xx interface figure 41 shows the interface between the adsp-21xx and the AD7723. the AD7723 is operated in mode 2 so that sco = clkin/2. for the adsp-21xx, the bits in the serial port con- trol register should be set up as rfsr = 1 (a frame sync is needed for each transfer), slen = 15 (16-bit word lengths), rfsw = 0 (normal framing mode for receive operations), invrfs = 0 (active high rfs), irfs = 0 (external rfs) and isclk = 0 (external serial clock). dr rfs sclk adsp-21xx sdo fso sco AD7723 figure 41. AD7723-to-adsp-21xx interface AD7723-to-sharc interface the interface between the AD7723 and the adsp-2106x sharc dsp is the same as shown in figure 41 but, the dsp is configured as follows: slen = 15 (16-bit word transfers), sendn = 0 (the msb of the 16-bit word will be received by the dsp first), iclk = 0 (an external serial clock will be used), rfsr = 0 (a frame sync is required for every word transfer), irfs = 0 (the receive frame sync signal is external), ckre = 0 clkin fsi sco fso (master) fsi (slave) doe (master & slave) sdo (master) sdo (slave) d1 d0 d15 d14 d15 d14 d1 d0 t 11 t 12 t 13 t 9 t 15 t 16 t 16 t 15 figure 40. serial mode 1 timing for two-channel multiplexed operation (the receive data will be latched into the dsp on the falling clock edge), lafs = 0 (the dsp begins reading the 16-bit word after the dsp has identified the frame sync signal rather than the dsp reading the word at the same instant as the frame sync signal has been identified), lrfs = 0 (rfs is active high). the AD7723 can be used in modes 1, 2 or 3 when interfaced to the adsp-2106x sharc dsp. AD7723-to-dsp56002 interface figure 42 shows the AD7723-to-dsp56002 interface. to inter- face the AD7723 to the dsp56002, the adc is operated in mode 2 when the adc is operated with a 19.2 mhz clock. the dsp56002 is configured as follows: syn = 1 (synchronous mode), scd1 = 0 (rfs is an input), gck = 0 (a continuous serial clock is used), sckd = 0 (the serial clock is external), wl1 = l, wl0 = 0 (transfers will be 16 bits wide), fsl1 = 0, fsl0 = 1 (the frame sync will be active at the beginning of each transfer). alternatively, the dsp56002 can be operated in asyn- chronous mode (syn = 0). in this mode, the serial clock for the receive section is input to the sco pin. this is accomplished by setting bit scdo to 0 (external rx clock). sdr sc1 sck dsp56002 sdo fso sco AD7723 figure 42. AD7723-to-dsp56002 interface AD7723-to-tms320c5x interface figure 43 shows the AD7723-to-tms320c5x interface. for the tms320c5x, fsr and clkr are automatically configured as inputs. the serial port is configured as follows: fo = 0 (16-bit word transfers), fsm = 1 (a frame sync occurs for each transfer). dr fsr clkr tms320c5x sdo fso sco AD7723 figure 43. AD7723-to-tms320c5x interface
AD7723 C22C rev. 0 grounding and layout the analog and digital power supplies to the AD7723 are inde- pendent and separately pinned out to minimize coupling be- tween analog and digital sections within the device. all the AD7723 agnd and dgnd pins should be soldered directly to a ground plane to minimize series inductance. in addition, the ac path from any supply pin or reference pin (ref1 and r ef2) through its decoupling capacitors to its associated ground must be made as short as possible (figure 44). to achieve the best decou- pling, place surface mount capacitors as close as possible to the device, ideally right up against the device pins. all ground planes must not overlap to avoid capacitive coupling. the AD7723s digital and analog ground planes must be con- nected at one place by a low inductance path, preferably right under the device. typically, this connection will either be a trace on the printed circuit board of 0.5 cm wide when the ground planes are on the same layer, or 0.5 cm wide minimum plated through holes when the ground planes are on different layers. any external logic connected to the AD7723 should use a ground plane separate from the AD7723s digital ground plane. these two digital ground planes should also be con- nected at just one place. separate power supplies for av dd and dv dd are also highly desirable. the digital supply pin dv dd should be powered from a separate analog supply, but if necessary dv dd may share its power connection to av dd . refer to the connection diagram (figure 44). the ferrites are also recommended to filter high frequency signals from corrupting the analog power supply. a minimum etch technique is generally best for ground planes as it gives the best shielding. noise can be minimized by paying attention to the system layout and preventing different signals from interfering with each other. high level analog signals should be separated from low level analog signals, and both should be kept away from digital signals. in waveform sampling and reconstruction systems the sampling clock (clkin) is as vulnerable to noise as any analog signal. clkin should be isolated from the analog and digital systems. fast switching signals like clocks should be shielded with their associated ground to avoid radiating noise to other sections of the board, and clock signals should never be routed near the analog inputs. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the AD7723 to shield it from noise coupling. the power supply lines to the AD7723 should use as large a trace as possible (preferably a plane) to provide a low impedance path and reduce the effects of glitches on the power supply line. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. +5v 10 m f 100nf 100nf 100nf 10nf 10nf 10nf 10nf 10nf 10 m f 220nf 10nf 1 m f ref2 agnd2 ref1 av dd 1 agnd1 agnd1 agnd agnd av dd av dd dv dd dgnd dgnd AD7723 analog ground plane AD7723 digital ground plane figure 44. reference and power supply decoupling
AD7723 C23C rev. 0 outline dimensions dimensions shown in inches and (mm). 44-lead plastic quad flatpack (s-44) 0.548 (13.925) 0.546 (13.875) top view (pins down) 1 33 34 44 11 12 23 22 0.033 (0.84) 0.029 (0.74) 0.398 (10.11) 0.390 (9.91) 0.016 (0.41) 0.012 (0.30) 0.083 (2.11) 0.077 (1.96) 0.040 (1.02) 0.032 (0.81) 0.040 (1.02) 0.032 (0.81) seating plane 0.096 (2.44) max 0.037 (0.94) 0.025 (0.64) 8 0.8 c3230C8C4/98 printed in u.s.a.

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